Projects target GaN processes, panel-level packaging

Article By : Graham Prophet

The GaNonCMOS project aims to develop reliable GaN processes, while the Panel-Level Packaging Consortium plans to implement PCB panel-level packaging.

Advanced PCB maker AT&S is joining two projects that aim to develop "the current state-of-the-art in manufacturing technologies."

The first project, according to the Austrian company, is the Horizon 2020 EU Research and Innovation programme, in which 11 key European participants will collaborate on the GaNonCMOS project. AT&S is also participating in the Panel-Level Packaging Consortium managed by Fraunhofer IZM.

Over the next four years, the GaNonCMOS project consortium intends to develop cost-effective and reliable GaN-based processes, components, modules and integration approaches. In particular, the project aims to exploit the energy-efficiency advantages of GaN, targeting the production of several demonstrators with GaN power switches and CMOS drivers, as well as new magnetic core materials that will enable switching frequencies up to 200MHz.

Together with optimised embedded PCB technology, the developments should lead to new integrated power components for low-cost, high-reliability systems, according to AT&S. Working alongside AT&S on this project are the University of Leuven, Epigan, Fraunhofer, IBM Research, IHP, Tyndall National Institute, PNO Innovation, Recom, NXP Semiconductors and X-FAB Semiconductor.

The first meeting of the project took place in January. The project aims to bring GaN power electronic materials, devices and systems to the next level of maturity by providing the most densely integration achievable, to build a new generation of densely integrated power electronics and highly reliable systems for energy intensive applications. The intent is to integrate GaN power switches with CMOS drivers using different integration schemes from the package level up to the chip level, including wafer bonding between GaN on Si(111) and CMOS on Si (100) wafers. GaNonCMOS is coordinated by Prof. Jean-Pierre Locquet from the Katholieke Universiteit Leuven.

Meanwhile, the Panel-Level Packaging Consortium has also been formed. It comprises international partners such as Intel, ASM Pacific, Hitachi Chemical, AT&S, Evatec, Nanium, Süss MicroTec, Unimicron, Brewer Science, Fujifilm Electronic Materials U.S.A., ShinEtsu, Mitsui Chemicals Tohcello and Semsysco. Together with Fraunhofer IZM as the development hub, the plan is to implement fan-out panel-level packaging (FOPLP), one of the newest packaging trends in microelectronics. FOPLP has a very high miniaturisation potential in both package volume and package density.

During the consortium’s two-year term, established techniques in wafer-level packaging will be transferred to a large panel format. The technological basis for FOPLP is a reconfigured, moulded panel with embedded components and a thin-film redistribution layer, which together yield an SMD-compatible package. The main advantages of FOPLP are a very thin, substrateless package, low thermal resistance and good RF characteristics. In addition, passive components such as capacitors, resistors, inductors and antenna structures can be integrated into the redistribution layer. This makes the technology suitable for creating multi-chip packages and System-in-Packages (SiPs).

Based on a panel size of 18in x 24in (a PCB manufacturing standard) or even larger sizes, lower packaging costs can potentially be achieved thanks to higher productivity.

This article first appeared on EE Times Europe