Intel exec sees huge potential for Moore’s Law post-CMOS
Moore’s Law has a long life, but pure vanilla CMOS process technology, not so much, a top fab executive from…
Chip design tool delivers tenfold performance boost
Synopsys recently upgraded its place-and-route chip design software, and its beta customers are already raving about the IC Compiler II’s…
Virtual design, verification for e-Mobility(2)
A big challenge in integrating systems is that components invariably come from multiple suppliers. This compromises safety and quality. At…
austriamicro’s Full Service Foundry introduces digital libraries
<!–BROKEN_TABLE_HIDDEN_BEGIN BROKEN_TABLE_ HIDDEN_END –> austriamicrosystems‘ business unit Full Service Foundry announced that it now offers digital libraries including standard cells,…
FPGA placement performs poorly: ICCAD
Timing-driven placement algorithms for FPGAs can be as much as 50 percent away from optimal results, according to a paper…
CSI to take part of Synopsys interoperability program
Circuit Semantics Inc. (CSI), a provider of modeling and characterization solutions for high-performance IC design, has joined the Synopsys in-Sync…
EDA industry reports another quarter of shrinking sales
EDA industry revenues have declined for three consecutive quarters, and were down 5.1 percent in the first nine months of…