Smart interposer drives high-performance, low-energy 3D IC

Article By : Junko Yoshida

The chip industry’s quest for 3D ICs has come a long way in the advance of 3D integration technology.

Chip stack

Jim Handy, analyst at Objective Analysis, told EE Times, “It’s confusing to a lot of people that the term ‘3D’ is used for two very different technologies.” There are “stacked chips,” and “chips with vertical structures,” he said. “The Leti’s technology is a chip stack.”

When chip stacks use TSVs, “they can use tens or hundreds of times as many interconnections as wire-bonded chips can,” said Handy. The key is that this reduces “the power used by each of these connections—due to two big reasons,” he added. First, there are no bonding pads or ESD protection—both of which would add a lot of lossy capacitance, he said. Second, “they can operate using unconventional signalling voltages, which can reduce power according to the V²/R law—power drops in proportion to the square of the signalling voltage,” he explained. “That’s very important.”

Smart interposer

Significantly, Leti’s 3D IC technology fundamentally differs from other 3D chips already available on the commercial market.

The difference lies in the interposer.

While commercial 3D chips—such as 3D memory ICs—are using “interposers that are pure silicon with no intelligence, “we are using a ‘smart interposer,” said Faynot.

A smart interposer, he said, means, “putting ‘active elements’ into the interposer.” Obviously, as a research institute, Leti needs to stay several steps ahead of the market, he added.

For example, Leti researchers are using active elements—like wiring—to connect elements within the interposer. Leti also plans to put photonic connections in the interposer, Faynot said. “We will be using light, not wire, for communication.” That technology, however, is still in development.

The use of the active interposer resulted in the 3D-NoC chip that “requires 20 times less energy for data transmission than chips placed on an electronic circuit board,” according to Leti.

Potential applications?

Who would benefit from 3D NoC technology? Lower energy consumption clearly makes the technology ideal for portable electronics, said Faynot. But most likely, FPGA vendors like Xilinx and Altera (now Intel)—always in hunt for higher performance—would be willing to try it, he added.

Handy said, “I think that the Leti approach should be well matched to high complexity ASICs and ASSPs, and perhaps even high-end CPUs and GPUs.”

But there’s a downside to proposing such a new 3D IC technology to chip designers, Faynot acknowledged.

The technology promises higher computing performance with substantially reduced power consumption, and gives designers the flexibility to integrate more devices from potentially different technologies—logic and memory. But such flexibility “challenges SoC designers to rethink their entire chip architecture,” Faynot said.

Ecosystem challenge

To prompt the semiconductor industry to embrace the new technology, “We need to create an ecosystem,” said Faynot. Chip designers must be assured access to the necessary tools and technologies that make it easy to try the 3D-NoC technology.

Leti learned a hard lesson from FD-SOI. Although the French research institute pioneered one of the key technologies in manufacturing SOI wafers, it spent the last 30 years watching the industry's painfully slow FD-SOI adoption.

Last year when EE Times asked Marie-Noëlle Semeria, CEA-Leti’s CEO, what Leti has learned from its own FD-SOI experience, she responded: "We could have tried to build a full ecosystem—involving all the key players—from the very beginning.”

Leti now says it won't make the same mistake again. Leti's 3D NoC technology can't remain as an exotic technology isolated in Grenoble.

A case in point is Leti's effort to gain active support and involvement from IRT Nanoelec, a research institute that brings together public and private partners to conduct groundbreaking R&D, especially in micro and nanoelectronics.

Leti's second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec, according to Leti.

In supporting the 3D-NoC technology, independent device manufacturers, CAD tool vendors such as Mentor Graphics, STMicroelectronics as a manufacturer, and EVG—a company with high-accuracy bonding technology—are already joining forces at IRT, explained Faynot.