Slim Flash process cuts down embedded layers by 20%

Article By : MagnaChip Semiconductor

MagnaChip plans to merge Slim Flash into various technologies, including BCD and high voltage.

Based on 0.13μm EEPROM, MagnaChip Semiconductor's new Slim Flash process technology promises to reduce the number of layers to be embedded by 20% and cut the manufacturing turnaround time by 15%.

The embedded NVM (Non-Volatile Memory) EEPROM process, which integrates logic, analog and memory into one chip, has been adopted in a wide range of applications such as automotive, MCU, touch IC and Auto Focus IC.

Qualification test for 0.13μm Slim Flash process technology was completed in both device performance and yield categories. All devices passed the WLR (Wafer Level Reliability) test, SRAM, and reliability test of standard cell library. In particular, high density EEPROM IP satisfied all categories related to endurance and data retention test.

Aside from the existing 0.13μm EEPROM, the South Korean manufacturer also plans to build a Slim Flash portfolio by merging Slim Flash into various technologies, including BCD and high voltage. MagnaChip is currently engaging with customers using the new technology, with several products currently in development.

Volume production of the Slim Flash process technology is expected to begin as early as the fourth quarter of 2016.