EUV rolls into TSMC’s 7+nm node in 2018

Article By : Rick Merritt

TSMC has used an unnamed “novel resist” chemical to replace five immersion masks with one EUV mask at pitches ranging from 26-30nm.

« Previously: TSMC unveils plans for 7+, 12, 22nm nodes
 

TSMC has disclosed plans to use EUV on an enhanced version of its 7nm process.

The foundry achieved similar yields using immersion and EUV steppers on a 7nm test chip. In addition, it hit 125W with its ASML 3350 EUV system, providing confidence it can hit about 250W for high volume manufacturing with EUV in 2019 on a 7+nm process.

Samsung announced late last year it plans to use EUV in a 7nm process that could be in production by 2019. “We believe we will be the first one” to use EUV in volume production, said TSMC’s Woo with risk production starting by June 2018.

The company did not detail exactly how it will use EUV steppers except to say it will be at multiple layers. Woo showed a demonstration of EUV 1P1E lines and spaces replacing 4P4E for immersion with “comparable yields and electric performance.”

“It’s important to be at least cost neutral [with EUV], you don’t have to wait for the ultimate goal,” said Jack Sun, a vice president of R&D at TSMC.

The foundry reported throughput between 1,458 and 1,633 wafers/day over three days with its ASML 3350 system. It aims to start risk production with the ASML 3400 stepper announced earlier this month, ramping to volume production in 2019.

TSMC used an unnamed “novel resist” chemical to replace five immersion masks with one EUV mask at pitches ranging from 26-30nm. Liu said the company currently expects EUV could compress as many as 16 immersion masks to four or five.

The enhanced 7nm process, in part, serves the needs of companies such as Apple that demand enhancements for each annual smartphone generation. The 7+ process promises 1.2x greater logic density and 10% more speed or 15% less power than TSMC’s first-gen 7nm node.

To migrate to the 7nm enhancement, designers “just need to comply with new EUV design rules,” said B.J. Woo, vice president of business development at TSMC. SRAM, analog and I/O components only need to be re-characterised, she added.

 
Next: TSMC's first-gen 7nm starts its ramp »