2017-09-14 - Rick Merritt, EE Times
TSMC Updates its Silicon Menu
TSMC added process and packaging variants to its broad foundry portfolio, but one analyst said some updated results were below…
2016-02-03 - Rick Merritt
Intel exec sees huge potential for Moore’s Law post-CMOS
Moore’s Law has a long life, but pure vanilla CMOS process technology, not so much, a top fab executive from…
2015-11-16 - Kevin Gibb
Examining metal eFuses
We first scrutinised the eFuses in Intel‘s 32nm high-k metal gate (HKMG) fabbed Westmere/Clarkdale processor (circa 2009). At the time,…
2012-10-19 - Luke Lang
Employ hierarchical methods for power intent specification(4)
Another feature of power intent integration is to resolve conflicting power intent rules and remove redundant ones. For example, the…