Synopsys develops interface, foundation IP for TSMC’s 7nm

Article By : Synopsys

TSMC also certifies the complete suite of Synopsys' digital, signoff and custom implementation tools for the 7nm node.

Synopsys has successfully taped out multiple customer test chips with DesignWare logic libraries and embedded memories for Taiwan Semiconductor Manufacturing Company's 7nm FinFET process.

The tapeouts mark a significant milestone in Synopsys' and TSMC's collaboration on the development of DesignWare Logic Library, Embedded Memory and Interface IP for the 7nm process. The collaboration extends Synopsys' long history of IP development on TSMC advanced FinFET processes for high-performance, low-power system-on-chips (SoCs).

TSMC has also certified the complete suite of Synopsys' digital, signoff and custom implementation tools for the 7nm node, enabling mutual customers to derive benefits of the new technology node using IC Compiler II.

To support TSMC's 7nm voltage operation, key features such as parametric on chip variation (POCV) specified with Liberty Variation Format (LVF) and advanced waveform propagation (AWP) technologies are supported in the Galaxy Design Platform. The platform is validated to handle the design rules and requirements of the full-coloured 7nm process, such as metal cut-awareness and reliability at all levels of the system-on-chip (SoC) design. The 7nm certification delivers routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE and interoperable process design kits (iPDKs).

Synopsys's DesignWare logic libraries and embedded memories are available now. The Star Memory System is also available now for all TSMC process technologies.