nvNITRO operates at 1.5M IOPS with 6μs latency

Article By : Dylan McGrath

Initial applications for nvNITRO accelerators include “anywhere you need very fast write speeds coupled with very low latency,” according to Everspin.

« Previously: Everspin's nvNITRO targets evolving MRAM market

Everspin has a fairly robust market for its first-generation products—the company also announced that JAG Jakob, which makes process control systems for pharmaceuticals and biotech facilities, is using its 16Mb MRAM. However, the market for the higher density ST-MRAM devices is still evolving.

“There is always some type of market adoption rate for new technology,” said Joe O’Hare, Everspin’s director of product marketing. “But we’ve been making very good progress here.”

Everspin continues to sample third-generation 256Mb ST-MRAM and is now testing 1Gb chips in house, according to O’Hare. The 1Gb chips are expected to be available by June.

“We have made progress as we have said in previous announcements, and I don’t think there is anybody close to us in terms of an actual product in customers’ hands,” he said. “Yes, it has taken a little bit of time, but I think we are executing to our roadmap. We see the opportunity to use these technologies in this technology in these performance and value added places until it becomes a little bit more of a mainstream technology.”

Conventional storage system accelerators generally require a power source such as supercapacitors or a battery to protect data as it's transferred from DRAM to non-volatile NAND flash. Because MRAM is ultra-low power, persistent and power-fail safe, systems using the nvNITRO can not only achieve higher performance, but do so with less power and space in storage racks, according to O’Hare.

The first two nvNITRO products, ES1GB and ES2GB, operate at 1,500,000 IOPS with 6 microsecond end-to-end latency, according to Everspin. They are offered in a half-height, half-length (HHHL) PCIe card with two access modes: NVMe SSD and memory mapped IO (MMIO). According to O’Hare, additional nvNITRO products with different form factors will also be available eventually.

Everspin also claims that the cycle endurance of ST-MRAM enables unlimited uniform drive writes per day, eliminating the need for complex wear levelling algorithms used in NAND flash based drives. There is also no degradation in read/write performance over time, according to the company.

Initial applications for the nvNITRO storage accelerators include “anywhere you need very fast write speeds coupled with very low latency,” according to O’Hare. “One application that we see, and a principal target of ours, is guys that are building very high frequency trading systems, where microseconds of difference in terms of confirmation of a trade, for example, seem to make a difference to these guys,” O’Hare said. “Those types of applications in the financial world are typically pushing the technology envelope across the board.”

Customers are currently testing nvNITRO devices, O’Hare said. General availability of the devices is expected in the second quarter, he added. Pricing information was not available.

In addition to the nvNITRO storage accelerators and the JAG Jakob design win, Everspin also announced compatibility for its ST-MRAM and Xilinx’s UltraScale FPGAs. Everspin said it would provide customers with a software script that modifies the existing Xilinx Memory Interface Generator (MIG) DDR3 DRAM controller to make it compatible with Everspin’s 256 Mb DDR3 ST-MRAM.

O’Hare said the arrangement, similar to a deal announced with the other big FPGA supplier, Altera, in 2014, is designed to give customers additional tools to help them use MRAM in their applications. “We’ve given our customers a lot of flexibility,” he added.

First published by EE Times U.S.

« Previously: Everspin's nvNITRO targets evolving MRAM market

Subscribe to Newsletter

Test Qr code text s ss

Leave a comment