Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs - EE Times Asia
Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designsIncreasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture, consisting of a jitter-attenuator and a frequency-synthesizer stage. Due to their […]
