New, complex electrical rule checking (ERC) requires a verification approach that can use physical and electrical information in combination to understand more complex connectivity and greater design context. In our latest white paper, “Advanced electrical rule checking in IC reliability verification,” we review the best strategies for automating sign-off quality verification for today’s most complex ERC at various design stages, including intellectual property (IP), block, and full-chip levels.
Topics covered include how to:
• Automate circuit verification for electrostatic discharge (ESD), electrical overstress (EOS), multiple power domains, advanced ERC, and many other reliability concerns
• Automate ERC flows for the most complex rules and conditions, such as latch-up, noise immunity, floating pins, cross-power-domain verification, and leakage current
• Achieve signoff-quality verification