SiFive has a new embedded RISC-V core and a simple way to access its processor cores on its website. What's different? You can get it for a one-time licensing cost, which however is in the mid-six figures.
Start-up SiFive has made its existing 32bit E31 core and a new 64bit E51 version available for one-time fees of about $300,000 and $600,000, respectively. An open source core called Rocket created by some of SiFive's founders remains available for free online. It can be used to configure and generate 32bit and 64bit processor cores.
The SiFive news comes just before the sixth workshop of the RISC-V open instruction set group, its first in China.
SiFive will have to compete with a wide range of cores from Cadence, Cortus, Imagination, Synopsys and Andes–which rolls out its first 64bit core next week. The existing players have more mature ecosystems and cores that also sell for less than a million dollars, said Linley Gwennap, principal of the Linley Group.
“I thought their original business model was the core would be open source, so they seem to have changed their business model…They are trying to innovate but at the end of the day everyone has costs,” Gwennap said.
“A year ago, there was quite a debate if people would license a core if there was a free version, [but now] we’ve seen significant demand for customers who don’t want an open-source version but one better documented with a company behind it,” said Jack Kang, vice president of product and business development at SiFive.
*Figure 1: SiFive provides just the processor core but researchers at Berkeley and elsewhere have released other elements, such as the TileLink interface (image: SiFive).*
The E31 and E51 come with a warranty the cores will hit a specified performance target as well as indemnification, documentation, test benches, constraint files and integration files. “The analogy here is with Red Hat that provides a package with support,” said Kang.
SiFive points to the value of making its silicon IP easy to access and royalty-free. Royalties are not a big issue for engineers who typically forecast their lifetime needs for a core and figure that into a total negotiated price," said Gwennap.
Datasheets and other detailed information to evaluate the cores, including FPGA bit-stream models and an evaluation version of functional, synthesisable RTL for the E31 are freely available on the company’s Web site. The site also lets engineers configure cores and buy them after agreeing to a seven-page licensing contract online.
“The ability to try, configure and buy a core over the Web is unheard of, and there’s no royalties so you don’t have to figure out how many you are going to sell,” said Kang.
“You can buy all sorts of software online and can even set up an Amazon data centre service with a few clicks, so why is the silicon IP industry so far behind?” asked Kang. “We have to get IP from others and it’s incredible how hard it is, so we have a chance to do something new for the industry,” he said.
Both the E31 and E51 can run at data rates up to 1.4GHz in a 28nm process. The E31 is roughly comparable to an ARM Cortex M3 or M4. The E51 creates a new entry-level for an embedded 64bit core below ARM’s Cortex A53.
Neither core runs Linux, SiFive plans to roll out a separate U54 core for standalone processors running Linux later this year. It may roll out an additional E-series cores before the end of the year.
FreeRTOS, Project Zephyr and Apache Minute OSes have been ported to the current E31 core. The RISC-V architecture now has available a GCC compiler for C, a GNU debugger and other peripheral tools. SiFive provides an SDK and an Eclipse-based development environment.
“There’s been huge progress in the RISC-V ecosystem,” said Kang.
The lack of royalties won’t curtail SiFive’s ability to grow, Kang said.
“We think there’s a huge market demand and we want to grow the ecosystem. We want more design starts rather than squeeze more money out of a declining number of design starts, and we have more cores and complex IP we can build,” he said.
SiFive also aims to make money helping design RISC-V-based SoCs. It launched an SoC platform in July 2016.
SiFive already has “multiple licensees of these cores and some cores not released yet, but Microsemi is our only public customer,” said Kang. It also has design partners who will offer its cores.
Microsemi is using RISC-V in imaging and video chips including its IGLOO2 and RTG4 FPGA platform. It is one of 60 members of the RISC-V Foundation along with Google, HPE, Microsoft, IBM, Qualcomm, Nvidia and Samsung.
Nvidia has announced it is developing a version of a 64bit RISC-V core to use as a controller in its future chips. The graphics giant evaluated options from ARC, ARM MIPS and Tensilica as well as a ground-up home-grown design.
“We have been excited by the growth and demand for RISC-V cores from our customers,” Flash Lin, chief operation officer at Faraday, said in a SiFive press release.
Proponents of RISC-V hope to tap into China’s growing electronics industry with their workshop in Shanghai next week. The event includes a speaker from the Chinese Academy of Sciences and Shanghai Jiao Tong University which is co-hosting the meeting.
WeChat and MeetUp groups have already sprung up in China, some attracting as many as 400 members, Kang said. About 400 engineers attended its last workshop, held in Silicon Valley.
The chief technologist of rival core designer Andes will speak at the RISC-V event but would not give details of his talk.
Andes will release its own 64bit embedded core, the AndeStar V5, at its own May 10 event in Shanghai. The chip supports up to 1,023 configurable interrupts and targets high-end networking, storage and automotive SoCs.