7nm-ready RAKs provide optimised RTL-to-GDS flow

Article By : Cadence

To accelerate the adoption of ARM's latest processors, Cadence has delivered new 7nm-ready Rapid Adoption Kits for the Cortex-A75 and the Cortex-A55 CPUs.

The Cadence Verification Suite and full-flow digital and signoff tools of Cadence Design Systems have been optimised to support ARM Cortex-A75 and Cortex-A55 CPUs, based on the ARM DynamIQ technology, and the Arm Mali-G72 GPU.

To accelerate the adoption of ARM's latest processors, Cadence delivered new 7nm-ready Rapid Adoption Kits (RAKs) for the Cortex-A75 and the Cortex-A55 CPUs, which include the DynamIQ Shared Unit (DSU) that provides a shared level 3 cache between the CPUs, and a 7nm-ready RAK for the Mali-G72 GPU.

The Cadence RAKs accelerate physical implementation, signoff and verification of 7nm designs, allowing designers to deliver mobile and consumer devices to market faster. With the delivery of the new RAKs, Cadence is also providing specialised technical support for ARM IP implementation.

The Cadence digital and signoff tools have been configured to provide optimal power, performance and area (PPA) results using the RAKs, which include scripts, an example floorplan and documentation for ARM's 7nm IP libraries.

The Cadence RTL-to-GDS flow incorporates the following digital and signoff tools in the RAKs: Innovus implementation system, Genus synthesis solution, Conformal logic equivalence checking, Conformal low power, Tempus timing signoff, Voltus IC power integrity solution and Quantus QRC extraction.

The Cadence Verification Suite that has also been optimised for Arm-based designs includes JasperGold formal verification platform, which enables IP and subsystem verification; Xcelium parallel logic simulation, which provides production-proven multi-core simulation; Palladium Z1 enterprise emulation platform, which includes hybrid technology integrated with ARM Fast Models; Protium S1 FPGA-based prototyping platform; vManager planning and metrics; Perspec system verifier; Indago debug platform; Cadence Verification Workbench; Cadence Interconnect Workbench; and the Verification IP Portfolio.